The present invention relates to a data path circuit in a NAND flash memory device. More particularly, the present invention relates to a data path circuit in a NAND flash memory device for reducing power consumed by a data output circuit when data are inputted.
Flash memory is a non-volatile memory for electrically erasing and programming data, and has the advantage of a random access memory RAM where data are freely written and erased and the advantage of a read only memory ROM where data can be maintained without a continuous power source. Hence, the flash memory has been widely used as a storage device for portable electrical devices such as a digital camera, a personal digital assistant PDA, and an MP3 player, etc.
A NAND flash memory device is a type of flash memory device, and includes a memory cell array, a row decoder and a page buffer.
The memory cell array has a plurality of word lines extended along rows, a plurality of bit lines extended along columns and a plurality of cell strings corresponding to the bit lines.
The NAND flash memory device performs a program operation for storing data in the memory cell array.
The program operation is divided into a command and address input interval, a data input interval and a third interval for programming inputted data in a memory cell array.
FIG. 1 is a block diagram illustrating a data input circuit in a common NAND flash memory device.
In FIG. 1, data inputted from an outside device (not shown) for program are temporarily stored in an input register (not shown), and then transmitted from the input register to a given circuit in the NAND flash memory device by a data input circuit 110. The transmitted data are provided to a page buffer (not shown) for the program operation of the NAND flash memory device.
FIG. 1 shows only the data input circuit 110 in the NAND flash memory device.
Generally, two 8 bit registers (first and second registers) are used to store the inputted 16 bit data.
The data input circuit 110 outputs in turn the data stored in the registers through two 8 bit data buses by using clocks CK_UP_LO and CK_UP_HI.
As mentioned above, the data are inputted from an outside device to the data input circuit 110 in FIG. 1 during the data input interval when the program operation is performed.
The flash memory device has a data input bus and a data output bus and uses a multiplex IO method for sharing a data input/output pad with these two buses. Accordingly, only the data input bus is used in the program operation. However, since the column address is connected to the data input bus and the data output bus, the data output bus performs a switching operation in response to a column address signal.
That is, a data output circuit for outputting data in the flash memory device operates even when the data output circuit does not have to operate while the data are inputted.
An internal address is changed in accordance with the toggle of an input control signal WE (write enable) and a read control signal RE (read enable), and so blocks related to the output of data switch the data output bus for output of data.
FIG. 2 is a timing diagram illustrating signals in the NAND flash memory device when data are inputted.
As shown in FIG. 2, signals 220 for output of data are activated in an operation interval 210 of an input register, wherein data are inputted during the operation interval 210.
In other words, an output operation of data does not have to be performed during the data input interval in the NAND flash memory device. However, in the common NAND flash memory device, the data output bus performs the switching operation during the data input interval. As a result, power is unnecessarily consumed.